Queen's University, Kingston, ON, Canada
CISC 324: Operating Systems
Winter 2021
Course Syllabus
The course presents the basic concepts of multitasking systems and the foundations of operating systems. It covers different topics such as process and thread management, interrupts handling, process
synchronization, memory management, and a little bit of operating system security. Also, the course provides practical mapping (through labs) of what is presented in the course lectures. The labs are
completely focused on process synchronization.
You are also invited to read the common syllabus elements related to accommodations, considerations, final exam
dates, and academic integrity.
Instructor
Dr. Karim Lounis (Postdorcoral fellow),
Email address: karim.lounis@queensu.ca,
Personal website:https://lounis.weebly.com/,
Lab: Queen's Reliable Software Technology,
Office: Goodwin 631,
Department: School of Computing.
Online live Sessions, over Microsoft Teams, are held on Mondays 12:30pm and Thursdays 1:30pm. These sessions, usually,
run for an hour. However, they may also run for less than an hour in case there are no further questions or discussions.
Lecture slides will be posted over OnQ. If you have questions and need clarifications about the lecture slides, then the live sessions will be the perfect location to get your questions answered and
clarified.
Teaching Assistants
The teaching assistants answer questions by email and/or during dedicated live sessions (upon request):
Guoliang Zhao (Ph.D. student),
g.zhao@queensu.ca
Michael Wrana (Master's student),
16mmw@queensu.ca
Anshul Pattoo (Undergraduate student),
anshul.pattoo@queensu.ca
Course Textbook
Operating System Concepts,
Ninth Edition (or newer), by Silberschatz, Galvin and Gagne, published by John Wiley. The eighth edition of this textbook is acceptable as well.
The publisher provides various resources on the
textbook website: click on the image of the textbook to find C/Java source code, a study guide, solutions to practice exercises, review questions, etc.
Course Workload
The course consists of 11 weeks of lectures (online sides + live sessions), 6 assignments (Q&As), 6 labs (Coding), and 2 term exams. The course grade distribution is presented in the last section of
this page (see bottom).
Course Schedule
| Weeks
| Dates
| Topics
| Slides
| Textbook Sections
|
| 1
| Jan 11, 13, 14.
|
Course started on Jan 11th
Course info: Introduction, motivation, overview, and review.
- Operating system overview: features and provided services.
- Review computer architecture (Von Neumann model).
- Single-processor system Vs multiprocessor system.
- Review of instruction execution cycle.
- Process management: processes, process states, and PCB (Process Control Block).
- Interrupt system: software and hardware interrupts.
- Context switching, interrupts with and without context switching.
- Concurrent processes: fake concurrency and real concurrency.
- Notion of threads: threads, threads vs processes, and user-level and kernel-level threads.
- Direct Memory Access (DMA), device controllers, and drivers.
|
Lecture_01
Lecture_02
Lecture_03
Lecture_04
Lecture_05
Lecture_06
1, 2, and 3.1-3.3.
| |
| 2
| Jan 18, 20, 21.
|
| 3
| Jan 25, 27, 28.
|
Assignment 1, Lab 1, and Lab 2 [due Friday, Jan 22nd at 9:00PM].
Process synchronization.
- Data race problem: Shared data corruption in concurrent programming.
- The critical section problem.
- Synchronization mechanisms: mutex and semaphores.
- Busy waiting and queue-based implementations for semaphores.
- Semaphores for process ordering and mutual exclusion.
- Binary and counting semaphores.
- Peterson's Algorithm for critical section problem.
- Classical synchronization problems: Readers/Writers, Dinning philosophers, and Producer/Consumer.
- Brief introduction on deadlock handling techniques.
- Resource allocation graphs.
|
Lecture_07
Lecture_08
Lecture_09
Lecture_10
Lecture_11
Lecture_12
5 and 7
| |
| 4
| Feb 01, 03, 04.
|
| 5 |
Feb 08, 10, 11.
|
Assignment 2 [due Friday, Feb 5th at 9:00PM].
- Deadlock prevention using static rules.
- Deadlock avoidance using Banker's algorithm.
- Deadlock detection and recovery.
Assignment 3 [due Friday, Feb 12th at 9:00PM].
|
Lecture_13
Lecture_14
Lecture_15
7, 8 and 9.
| |
| ---
| Feb 15, 17, 18.
| Family Day + Reading Week, No Class
|
|
|
| 6
| Feb 22, 24, 25.
|
Term Exam 1 (Feb 22nd) [90 minutes within a 12-hour timespan]
Memory management.
- Memory pyramid, memory types, and backup memories.
- Review program processing cycle (Compile, Linking, Loading and executing).
- Dynamic linking and dynamic loading.
- Logical and physical addresses.
- Address binding: Compile time, load time, and runtime address binding.
Lab 3 [due Friday, Feb 26th at 9:00PM].
|
Lecture_16
Lecture_17
Lecture_18
| |
| 7
| Mar 01, 03, 04
|
- Memory allocation strategies (contiguous and noncontiguous).
- Single-level paging memory management scheme.
- Virtual address translation in paging.
- Translation Look-aside Buffer: TLB-hit and TLB-miss.
- Multilevel paging memory management system.
Lab 4 [due Friday, Mar 5th at 9:00PM].
- Segmentation memory management scheme.
- Segmentation with paging.
- Page fault and segmentation fault
Assignment 4 [due Friday, Mar 12th at 9:00PM].
- Virtual memory.
- Page fault handling.
- Page replacement algorithms
- Thrashing and prevention techniques (working set and PFF)
Process synchronization (Con't)
- Monitors for process synchronization
- CPU scheduling algorithms: FCFS, RR, PRIORITY, SJF, SRTF, MLQ, and MLFQ.
Assignment 5 [due Friday, Mar 19th at 9:00PM].
|
Lecture_19
Lecture_20
Lecture_21
Lecture_22
Lecture_23
Lecture_24
Lecture_25
Lecture_26
Lecture_27
8 and 9
| |
| 8
| Mar 8, 10, 11
|
| 9
| Mar 15, 17, 18
|
| 10
| Mar 22, 24, 25.
|
Interprocess Communication
- Message passing for process communication and synchronization, Sockets, and RPCs.
Hard Disk Drive scheduling
- Disk space allocation.
- HDD scheduling algorithms.
Security in Operating systems
- Security threats and aspects.
- Security services in OS: authentication, confidentiality, integrity, availability, and non-repudiation.
- OS security threats
- OS security tools: Anti-virus, anti-spyware, IDS, IPS, firewall, and honypots.
- Some OS attacks: Buffer overflow on the stack, overflow on the heap, and integer overflow.
Lab 5 and Assignment 6 [due Friday, Mar 26th at 9:00PM].
|
Lecture_28
Lecture_29
Lecture_30
|
3, 6, 14, and 15
|
| 11
| Mar 29, 31, Apr 1.
|
Term Exam 2 (Apr 1st) [90 minutes within a 12-hour timespan]
Lab 6 [due Friday, Apr 9th at 9:00PM].
|
| |
Assignments
Assignment general directions:
When an assignment is released on this website the course instructure will let you know through email. You will get a posting-notification on OnQ anyways.
Assignments must be submitted in PDF format. No other format is accepted. Late work will certainly be subject to a penalty. See late submission policy.
Assignments are to be performed individually. Solutions will be available on onQ after the assignment due date.
Assignment documents:
-
Assignment 1 (Assignment_1.pdf) [due Jan 22nd]
This assignment covers computer architectures, instruction execution cyles, processes management and interrupts. There are theoritical questions as well as practical questions.
-
Assignment 2 (Assignment_2.pdf) [due Feb 5th]
This assignment covers process synchronization, mainly, process precedence graphs, CoBegin and CoEnd program constructs, and semaphore usage for code synchronization.
-
Assignment 3 (Assignment_3.pdf) [due Feb 12th]
This assignment covers process synchronization, mainly, a classical synchronization problem, critical section problem requirements, process precedence graphs, CoBegin and CoEnd program
constructs, and some deadlock avoidance using RAGs (Resource Allocation Graphs).
-
Assignment 4 (Assignment_4.pdf) [due Mar 12th]
This assignment covers memory management, in particular, virtual and physical address, fragmentation, paging, segmentation, and segmentation with paging.
-
Assignment 5 (Assignment_5.pdf) [due Mar 19th]
This assignment covers memory management, in particular, virtual memory, segment fault, page fault, effective memory access time with page faults and TLB, and page replacement algorithms.
-
Assignment 6 (Assignment_6.pdf) [due Mar 26th]
This assignment covers monitors, CPU scheduling, and OS Security.
Labs
Labs general directions:
When a Lab is released on this website the course instructure will let you know through email. You will get a posting-notification on OnQ anyways.
You should submit (upload) your lab (Zipped file) onto OnQ before or by the due date. Depending on which group you belong to in the class, your lab (source codes and readme.txt file) will be reviewed and
marked by an assigned TA. Late work might not be accepted. See late submission policy.
Labs are to be performed individually. Solutions are not released. Discussing your lab solution is welcome though.
CISC324 does not have formally scheduled lab sections, so you may complete lab work anytime but not beyond the due dates. If you run into difficulty with a lab, contact a TA by email.
Lab Instructions and Files:
- Lab 1 (Lab_1.pdf) [due Jan 22nd]
In this lab, there are two exercises. In the first exercise you will be using the C-program in eXer_1.c. In the second exercise, you will be using two C-programs eXer_2.c and
count.c.
- Lab 2 (Lab_2.pdf) [due Jan 22nd]
In this lab, there is only one exercise. During this lab, you will be using the Java class file ThreadAttacker.java and the Java class file
ThreadBot.java.
- Lab 3 (Lab_3.pdf) [due Feb 26th]
This lab is challenging because it is your first time writing synchronization code. As a first step, study and execute the given code where readers have priority (course reader page 29). Make sure
that you can tell from looking at the output that readers are indeed getting priority. Then plan how to create code that gives priority to writers. The Java codes for readers having priority are:
MainMethod.java which is the main class, Reader.java which defines the readers class, Writer.java which defines the writers class, RandomSleep.java which defines a
class for random sleeping methods (you will need that to simulate a reader that is reading, a writer that is writing, and a reader/writer that finished then came back to read/write again), and
Synch.java which defines the class of semaphores that you will be using.
- Lab 4 (Lab_4.pdf) [due Mar 5th]
This lab consists of implementing a synchronization code using Java semaphores to simulate the cars traffic around two regions. A car is initially driving around
Barriefield (East of Kingston) then crosses a causeway westbound to Kingston to enter a petrol station and fill up the fuel tank. Once done, the car drives back
to Barriefield crossing the causeway eastbound. Because of roadworks, there is onlt one lane that can be used to cross westbound or eastbound. You are given the
MainMethod.java file that contains the main method, the Car.java file that contains the car code, the Synch.java file that will contain the
semaphores and shared counters, the Semaphore.java that contains the semaphore class, and finally the TimeSim.java file that contains an accurate
time simulation written by Professor Blostein. The simulated time advances after all threads have reached a sleep() or acquire(). The implementation of
timeSim needs an exact count of the number of threads. Therefore, every thread you create has to begin by calling Synch.timeSim.threadStart() and has to
end by calling Synch.timeSim.threadEnd(). The car thread code in Car.java shows how to do this. Note that because Java's built-in sleep() method results
in inexact timing. For example, if two threads execute a sleep instruction at the same time, the thread that executes sleep(20) may wake up before the thread that executes sleep(10), you are provided
with the
TimeSim.java file to have a better precision in your simulation.
- Lab 5 (Lab_5.pdf) [due Mar 26th]
This lab consists of implementing a synchronization code using Java Monitors. It consists of two exercises: (1) The first exercise consists of writing synchronization code using Java Monitors for
the readers-writers problem (starvation free solution). You are given the solution with readers having priority in the following Java files: MainMethod.java, Reader.java,
Writer.java, SharedDataStruct.java, and rwMonitor.java. You have to modify the code so that the behaviour reflects a
starvation free solution (2) The second exercise consists of correcting a synchronization code using Java Monitors for the Bounded Buffer problem. You are provided with the following Java
files:
MainThread.java, Producer.java, Consumer.java, and Buffer.java.
- Lab 6 (Lab_6.pdf) [due Apr 9th]
This lab consists of implementing a distributed application using Java sockets and Java RMI(Remote Method Invocation) message passing technologies to compare
multiple page replacement algorithms. You are provided with the following two java applications: (1)T1.java, T2.java, and (2) Client.java,
Server.java, Server_Interface.java. You can use those files as your building blocks for the lab. At the end of this lab, you will learn how to
write code that involves multiples processes/threads that communicate and cooperate over the network using message passing to share data and set up
synchronization.
Late Submission Policy (for Assignment 2 to 6, and Lab 3 to 6)
- If you submit your work 15 minutes after the deadline, then you lose 5% of the total grade.
- If you submit your work 24 hours after the deadline, then you lose 10% of the total grade.
- If you submit your work 48 hours after the deadline, then you lose 20% of the total grade.
- If you submit your work 72 hours after the deadline, then your submission will not be considered.
Grade distribution
Assignments are worth 22% of the course grade. The grade breakdown is as follows:
- Assignment 1 weights 3.5%.
- Assignment 2 weights 4.0%.
- Assignment 3 weights 2.5%.
- Assignment 4 weights 5.0%.
- Assignment 5 weights 4.0%.
- Assignment 6 weights 3.0%.
Lab are worth 28% of the course grade. The grade breakdown is as follows:
- Lab 1 weights 3.0%.
- Lab 2 weights 2.0%.
- Lab 3 weights 5.0%.
- Lab 4 weights 6.0%.
- Lab 5 weights 6.0%.
- Lab 6 weights 6.0%.
Term exams weight 25% each.